One type of modern nonvolatile memory is the EPROM or EEPROM device that uses floating gate structures. The memory cells within the devices use general hot electrons for programming from the drain side and use Fowler-Nordheim tunneling for erasure from the source site. These devices are also known as flash memory devices. The gate structure for these devices is typically a stack configuration comprising a floating gate and a control gate separated by an insulator layer. The gate stack is typically disposed on a tunnel oxide layer.
Flash memory device memory cells comprise the gate stack structure discussed above. These memory cells make up a memory array region of the flash memory device. In addition to the portion of the chip utilized to form the memory array itself, flash memory devices require a substantial amount of support circuitry integrated within the same semiconductor chip. This support circuitry may comprise, for example, a read/write/erase control circuit, a decoder, or other necessary controlling components. This control circuitry occupies a region of the device hereafter referred to as a periphery region. Thus, flash memory devices comprise a memory array region and a periphery region. The periphery of a flash memory device further comprises a high voltage area and a low voltage area.
During the formation of a flash memory device, it is generally necessary to form structures and/or layers of semiconductor material on one region of the flash memory device that are not present on the other region, or to form structures and/or layers that require different dimensions on different regions of the flash memory device. For example, the gate stack described above may require the deposition of layers not required in the support circuitry of the periphery region.
These differences in the formation of semiconductor structures between the two regions of a flash memory device require the addition of several semiconductor processing steps, with the accompanying increase in the time and cost of processing. For example, three different thicknesses of dielectric material are required after the formation of the polysilicon gate structures present in the memory array region of flash memory devices. The first dielectric thickness is that placed over the floating gate structures. A second and third dielectric thicknesses are disposed in the periphery region of the device. The thickness of dielectric material needed to insulate portions of the support structures in the high voltage periphery region of the substrate and the thickness required to insulate portions of the support structures in the low voltage peripheral region is significantly different. In current semiconductor fabrication processes, three distinct pattern, etch, and removal sequences must be utilized to achieve these three varied thicknesses of the dielectric material. The additional processing poses significant constraints on the processing time and per unit cost required to fabricate flash memory devices.